1. Field of the Invention
The present invention relates to a thin film transistor array in which a pair of thin film transistors is disposed in parallel for each picture cell of a liquid crystal element for driving the latter in an active matrix condition. The array incorporates a structural bypass technique for circumventing shorts during the processing of the array without increasing the number of power supply terminals necessary to drive the array.
2. Prior Art
As illustrated in FIGS. 5 and 6, a known thin film transistor array having thin film transistors (referred to as TFT hereinbelow) disposed in pairs for each liquid crystal picture cell includes a substrate 1 of a glass, and a plurality of gate buses 2 and source buses 3 perpendicularly intersecting each other and disposed on the substrate, both of the buses being made of molybdenum. The gate bus 2 and the source bus 3 intersect each other at a cross-over point 4. The source bus 3 extends over the gate bus 2 and the two buses 2 and 3 are electrically insulated from each other by an insulation film 5 as shown in FIG. 5. The insulation film 5 is composed of two layers having a first insulation film member 6 of silicon nitride and a second insulation film member 8 of hydrogen amorphous silicon applied over the gate bus 2 as shown in FIG. 6. The second insulation film member 8 is formed simultaneously with a semiconductor film for TFT 7 shown in FIG. 5. A passivation film 9 shown in FIG. 6 extends on and over the entire upper surface of the substrate 1 covering the source bus 3 layer. The passivation film 9 is made of a material such as silicon nitride.
The gate bus 2 has a gate branch line 10 extending therefrom at a position near the cross-over point 4, and the source bus 3 has a pair of source branch lines 11, 11 both leading into the TFT 7 as shown in FIG. 5. Therefore, the TFT 7 is disposed adjacent to the cross-over point 4. The TFT 7 is a pair of TFT members each disposed perpendicular to the source bus 3 and parallel to the gate bus 2 and a picture cell electrode. The TFT pair share a common gate electrode, a pair of source electrodes, a pair of drain electrodes and a common semiconductor film. Either one or both of the TFT pair drives one picture cell of the liquid crystal display element. The TFT 7 is fabricated with a gate insulation film and a semiconductor film disposed over the common gate electrode. The gate insulation film is disposed at the same time the first insulation film member 6 is disposed over the gate bus for the crossover point 4. The semiconductor film is disposed over the gate insulation film member at the same time the semiconductor film 12 and the second insulator member 8 of the crossover point 4 are formed. Disposed on the semiconductor film of the TFT are the two source electrodes formed of aluminum simultaneously with the source bus 3 and the two drain electrodes. The passivation film 9 shown in FIG. 6 is disposed on and over the electrodes. The TFT 7 further includes a light shield 13 made of aluminum, for instance, which is disposed on and over the other components.
The thin film transistor array of such a construction has a drawback in that a short circuit in the array takes place almost inevitably due to various physical defects created during the manufacturing process thereof. Namely, a short circuit could occur at the cross-over point 4 where the gate bus 2 and the source bus 3 intersect with each other, or between the gate electrode and the source electrode of the TFT, for example. A short circuit defect results in a linear or a spot linear defect of the liquid crystal display element, thereby deteriorating its display characteristics.
To this end, it is customary to take measures to repair the short-circuited portion for eliminating the liner or the spot picture defect. A conventional repair method is performed as follows. Before the final passivation film 9 is applied to the substrate, an isolation test is performed between one terminal G1 of the gate bus 2 and one terminal S1 of the source bus 3 to verify if a short has developed between the gate bus 2 and the source bus 3. If a short circuit is detected therebetween, the source bus 3 being the upper layer bus, is severed by means of a laser beam at a position a in FIG. 5 located between the two source bus branch lines 11. Laser trimming can be accomplished using a YAG laser. Once position a on the source bus is opened, a second isolation test is performed between the terminal G1 of the gate bus 2 and the terminal S1 of the source bus 3. If a short circuit remains evident therebetween, the source bus 3 is severed at a position b in FIG. 5, located between one source branch line 11 and the cross-over point 4. The cut at position b will open any short circuit, if any, developed at a point A on the TFT 7 in FIG. 5. The isolation test is repeated between the two terminals G1 and S1, and if a short is detected therebetween, the source bus 3 is severed at a position c in FIG. 5 located between the cross-over point 4 and the terminal S1 of the source bus 3. This step in the repair process serves to cut off a short circuit, if any, developed at a point B, indicated in FIG. 5, on the cross-over point 4. If the second and subsequent isolation tests prove that there exists no short between the Terminal G1 of the gate bus 2 and the terminal S1 of the source bus 3, the isolation test is performed between the terminal G1 of the gate bus 2 and the other terminal S2 of the source bus 3. If a short is detected therebetween, the TFT 7 may be shorted at a point C in FIG. 5. The source bus 3 is severed at a position d in FIG. 5. Following this sequence of isolation tests, any short circuit developed at points A, B and C in FIG. 5, are completely disconnected from the source bus 3. Therefore, the short is detected during fabrication and eliminated prior to driving the liquid crystal display element of the final product. In this way, power can be supplied to the member of the TFT pair and thus avoids the subsequent occurrence of spot picture defects, because it rarely occurs that both of the TFT members are short-circuited simultaneously. The above-described repair is followed by application of the passivation film 9 over the entire surface of the substrate 1 and then the light shield 13 over the TFT 7 component.
According to the conventional repairing method described above, each end of the source buses 3 needs to have power-supplied from the opposite end terminals S1 and S2 which doubles the number of required power supply terminals necessary. Further the power supply terminals are located often too close to each other which creates a potential for a short circuit therebetween. Moreover, if a short circuit is detected at more than two points on source bus 3, the power cannot be supplied to any portions disposed between the short-circuited points. Finally, if shorts are detected at points which are located relatively remote from each other, a series of spot picture defects will develop in succession and thus often lead to a quasi-linear picture defect.